Information processing system

ABSTRACT

An information processing system having a plurality of subsystems including a display, a memory, and a manually operable data and control function entry device for interactive text processing by an operator via a keyboard whereby text entered on the display is modifiable under the control of the operator. Each of the sub-systems is interconnected to each of the other subsystems by means of a communications bus which includes a data bus, a special control and indicator bus, an address bus and a timing bus. Digital information indicative of the text to be entered or operated on in the system is available simultaneously to all sub-systems by means of the data bus. The special control and indicator bus transmits signals between sub-systems, which signals are operator generated, or sub-system generated to enable pertinent sub-systems to receive or transmit information relevant to the performance of its function. The address bus provides a means for any sub-system in the system to address any other subsystem in the system or for any sub-system to cause any other sub-system to transmit commands or data to a third sub-system, which events may occur asynchronously with respect to system timing. System timing information is provided to the sub-systems by means of the timing bus which transmits information necessary to divide the system timing into three major time frames which are display time, retrace time, and flyback time. Each time frame is furthere subdivided into time periods (MAC times) which time period corresponds to the time utilized for memory addressing each MAC time is further subdivided into eight time slots (T0T7), with each time slot being generated by eight Delta T time pulses. The MAC time signals generate retrace and flyback signals which are transmitted over the timing bus. The timing bus also transmits a memory clock signal which occurs within a time slot and is gated under the control of the Delta T time pulses as well as a strobe signal which is enabled during each time slot under the control of the Delta T time pulses. Information transmission between sub-systems is time shared on the communications bus in accordance with pre-allocated concurrence of time frame, time period (MAC time), and time slot with display time generally utilized for the transmission of text dependent information and non-display time with transmission of non-text dependent information. The information processing system is an organization of distributed text processing systems with each sub-system performing a small number of specific operations on text, with each particular sub-system being activated whenever it detects, by monitoring the communications bus, a particular sequence of information including the pertinent time frame, time period (MAC time), and time slot necessary to the performance of the function.

United States Patent [191 Goldman 3,815,104 June 4, 1974 Primary Examiner-Paul J. Henon Assistant E.taminerPaul R. Woods [57] ABSTRACT An information processing system having a plurality of sub-systems including a display, a memory, and a manually operable data and control function entry device for interactive text processing by an operator via a keyboard whereby text entered on the display is modifiable under the control of the operator. Each of the sub-systems is interconnected to each of the other sub-systems by means ofa communications bus which includes a data bus, a special control and indicator bus, an address bus and a timing bus. Digital information indicative ofthe text to be entered or operated on in the system is available simultaneously to all subsystems by means of the data bus. The special control and indicator bus transmits signals between subsystems. which signals are operator generated, or subsystem generated to enable pertinent sub-systems to receive or transmit information relevant to the performance of its function. means for any sub-system other sub-system in the s The address bus provides a in the system to address any ystem or for any sub-system to cause any other sub-system to transmit commands or data to a third sub-system, which events may occur asynchronously with respect to system timing.

System timing information is provided to the sub-systems by means of the timing bus which transmits information necessary to divide the system timing into three major time frames which are display time, retrace time. and flyback time. Each time frame is furthere subdivided into time periods (MAC times) which time period corresponds to the time utilized for memory addressing each MAC time is further subdivided into eight time slots (T -T with each time slot being generated by eight Delta T time pulses. The MAC time signals generate retrace and flyback signals which are transmitted over the timing bus. The timing bus also transmits a memory clock signal which occurs within a time slot and is gated under the control of the Delta T time pulses as well as a strobe signal which is enabled during each time slot under the control of the Delta T time pulses.

Information transmission between sub-systems is time shared on the communications bus in accordance with pre-alloeated concurrence of time frame. time period (MAC time), and time slot with display time generally utilized for the transmission of text dependent information and non-display time with transmission of non-text dependent information.

The information processing system is an organization of distributed text processing systems with each sub-system performing a small number of specific operations on text, with each particular subsystem being activated whenever it detects. by monitoring the communications bus, a particular sequence of information including the pertinent time frame, time period (MAC time). and time slot necessary to the performance of the function.

6 Claims, 68 Drawing Figures l2 i8 32 34 36 48 38 I l l H TYPEWR'TER POSITION MAGNETIC SELECTHNSERT s lrg t ign'roa DISPLAY 'NDICATOR tNDICATOR EDIT/MERGE PE L D A r A e u s g l0 3 i L SPECIAL CONTROL AND INDlCATOR BUS I OPERATOR L ADDRESS AND COMMAND BUS as j L T M I N G s u s Q j KE BOA D CLEAN TAB PAGINATE pnwrza INTERFACE MEMO HYPHEN I l i i I f f f} 46 44 42 50 KEYBOARD ,4

PATENTEDJUII 4 I974 SHEEI 07 0F 31 SPECIAL CONTROL AND INDICATOR BUS DISPLAY TIME PIN No T T T T T T T T wRITE WRITE 9 SEEGEOJT gQTSTEIIINTTO A S T INTO THE ADDREss 3 INDICATOR IE Q S MEMORY MEMORY LOCATION COMMAND HYPHEN HYPHEN II ERAsE COD I BLANK END H LOAD LOAD 4| ,WCATOR ON g LAIISIECATOR sELECT COLUMN COLUMN BUS ,ND'CATOR INDICATOR CuRsOR CuRsOR EgfiEfl JUST'FY DECREMENT INCREMENT INCREMENT 45 mm uNIT SPACE COMMANO ROW ROW ROW IND'CATOR COUNTER CuRsOR CuRsOR CuRsOR I CLEAR 46 V%\FIQTDNUE SE25 SVQDIXIHNUE C EMENT gqociluEwrsNT COLUMN ICNSFUEMSNT INDICATOR INDICATOR CuRsOR CuRsOR Qg Q CURSOR MEMORY PRESENT 49 $325 QBBK I L D ON LINE IS I III I B I T N M FOLLOWED DIC OR EgLQJSLS BY A LINE RIGHT HAND AT RIGHT 5O LIMIT AT QSQ CHARACTER gfi END OF $9 w END OF INDICATOR INDICATOR CONTROL RARACRARR EOuALs JUSTIFY (LOCK 288 UNS ZONE KEYBOARD) EDIT/ ACTIVE ACTIvE ACTIvE 5 MERGE BLANK BLANK BLANK PROTECT Egg INHIBIT CI-IAR AOD BUSY INDICATOR INDICATOR INDICATOR INDICATOR INDICATOR KEYBOARD INDICATOR MEMORY NUL BLANK DI LAYABLE LEFT HAND c sTROBE AUTO CHAR 52 MARGIN CLEAN-UP MARCIN DELETE BUSY INDICATOR CHAR INDICATOR NDICATOR INDICATOR CARD JUSTIFY INDICATOR PATENTEDJIIII 4IIII4 sum 08 or 31 SPECIAL CONTROL AND INDICATOR BUS RETRACE FLYBACK PIN No MAC I MAC 2 MAC 3 OTHER INHIBIT Row ADO (T2) 39 MEMORY LINE 0 (T4) END MEMORY MEMORY LINE 59 ACTIVATE HYPHEN INHIBIT ERASE LINE 59(1' (T L'GHT CONTROL RET- FL? MA :4 T

RET-FLY-MAC 3 -T3 RECIRCULATE LOwER 45 BUFFER FOR ONE LINE (T6) TOGGLE UPPER AND 46 LOWER BUFFER (T6) RING THE BELL DISPLAY VERTICAL INHIBIT ROw COUNT MARGIN (T I 49 SIGNAL (T2) LOWER VE'RTML MARGIN INDICATOR MAc O-T DISPLAY MEMORY (T6) END OF TERM cLEAN-uP 5O DISPLAYAEILE REGION MERGE 2 (T1) UPPER VERTICAL MARGIN DISPLAY MEMORY (T6) MEMORY BUSY (T 52 c sTROBE IND (T4) CURSOR LINE 59 (T5) Row DELETE (T3) LINE 5a IND (T6) PATENTEIIIIIII 4 I914 sum -IIsIIr 3I SPECIAL CONTROL AND INDICATOR BUS RETRACE FLYBACK g MAC MAC 2 MAC 3 OTHER AuTO MARGIN MAC9-T2 39 INHIBIT Row A00 (T2) PRINTER BUSY (T3) PRINT BUSY MACQB INHIBIT TA E COMMAND(T|) TAPE BUSY T 41 INHIBIT ROLLuP (T2) TAPE AFTER 3) READ'NG PAGE 5 TAPE WRITING (T5) RESET TAPE INHIBIT (T7) INCR Row CURSOR W/PLATEN MAC9-Tz DEcREMENT Row l UNIT CHAR DELETE CURSOR w/PLATEN MACS-T4 45 FROM KYBD- (T3) RESET COL TO ZERO MAC 9-T DISPLAY DEC TAB RESET ROW CURSOR(OJMAC9- 6 INHIBIT OVERSTRIKE (T5) RESET Row CURSOR (58) AIDS-T 46 I UNIT CHAR ADD FROM KEYBD (T3) RING THE BELL 49 SIGNAUTZ) c STROBE IND. (T3) TERMINATE CLEAN-UP LOAD ROw CURSOR 5O MERGE (T2) MAC9-T3 BACKSPACE INDICATOR SPACING BETWEEN (T3) LINES MACOTZ VERT MARGIN SET (T 5] (TI) (SPA)CE BAR INDICATOR MERGE TEXT (T 1 2 T a SELECT TEXT (T 3 PRINT (T7) MEMORY BUSY (T I 52 CHAR IND (T3) DON T ISSUE COMMAND DEC TAB SET (T2) HAIIENTEDJIIII 4 I924 sIIIII 100F 3I ll ig. in

vi 2 TRANS RECEIVING COMMAND COMMAND E ELE CARD OR DATA ON PIN NO. COMMENT ANY MEMORY CHARACTER CPINI (T7) AFTER ADDRESSING THE CARD CARD ADD MEMORY ANY MEMORY CHARACTER CPINZ (T7) AFTER ADDRESSING THE CARD CARD DELETE MEMORY ANY MEMORY 5865f? CPIN3 (T7) AFTER ADDRESSING THE CARD CARD DELETE MEMORY ANY MEMORY Row ADD CPINS (T7) AFTER ADDRESSING THE CARD CARD MEMORY MAC3-RETRACE ANY COMMUNICATIONS Row CARD BUS DELETE FLYBACK-C PIN 52 ANY MEMORY 3125 CPIN 55 (T5) AFTER ADDRESSING THE CARD CARD MEMORY DOwN SHIFT DOwN AFTER ADDRESSING THE 3%, E E STEP LOWER CM 55 (T5) MEMORY FOLLOWING THE euFFER COMMANo INITATE SHIFT OOwN COMMAND ANY MEMOR INITATE SHIFT CPIN 57 (T5) AFTER ADDRESSING THE CARD CARD OF COMMAND MEMORY SHIFT u MEIE R$5EESWFKJ A R PI H 5 ,533 Y STOP LOwER C N56 (T7) INITIATE SHIFT OR BUFFER COMMAND COMMAND PATENTEDJUH M974 1815104 saw 12 or 31 DATA BUS z I 3 I9I Jig. 12 2 HEIGHT RoIvI/ DATA SELECTOR TGI-I HIGH RS I99 I93 e BIT PARALLEL -|92 IvIuLTIPLExER lN/ PARALLEL OUT REGISTER A90 WE CLQCK Tp T MXS INH III/RITE 4 g |95 G INH WRITE I AcTIvE BLANK g4 2 h CODE TO DATA BUS AT T4 5 (D I74 I72 I98 |96 L I73 r I cR DECODER AcTIvE (CARRIAGE RET) RS BLANK KUL (UNDERLINE) ENCODER I52 v I I5)6 I97 READ LKUL ENABLE I65 A ECR 4 woRo READ/ I59 REGISTER SELECT 1 WRITE -KMB A wRITE DECODE @O I5 COMP ENABLE I ,9 HEAD LO-{AR SELECT I I: |66 4-YOVF D Z I I50 u 62 g D 3 --I5| Q 2 A JAIIF 5 In In 5 N I q TBIT ALPHA NUMBEHIC coo: CHARACTER l4 PLUS 8TH BIT SPACE BIT me STROBE KEYBOARD PATENTEBJuu 41914 saw many NH Em PATENTEDJUN 41914 saw 19mm nSOU 30m EEO mmm 0500 JOU mom 

1. In a text processing system which includes a keyboard subsystem through which an operator can enter information into the system, a memory sub-system for storing information, a display sub-system for providing a visual display of information previously entered into the system and a printer sub-system for providing a typed or printed output from the system, and in which each of the sub-system receives signals indicative of text of control functions from other sub-systems in the system and each of the sub-system provides signals indicative of text or control functions to other sub-systems in the system, the improvement comprising: a communications bus; timing means for generating a recurring cycle of timing signals; means for applying the timing signals generated by the timing means to the communications bus, and a plurality of input-output means each associated with a respective one of the sub-systems for connecting the sub-system to the communications bus, each input-output means responsive to the timing signals on the communications bus for connecting its respective sub-system to the communications bus during predetermined portions of the cycle of timing signals, whereby its respective sub-system can receive signals from another of the sub-systems and provide signals to another of the subsystems during the predetermined portions of the cycle of the timing signals.
 2. The text processing systems of claim 1 in which the communications bus includes a timing bus section, the means for applying the timing signal to the communications bus comprises means for connecting the signals generated by the timing means to the timing bus, and in which each of the input-output means is connected to the timing bus to receive the timing signals from the timing means.
 3. The text processing system of claim 2 in which the timing means comprises means for generating a recurring cycle of timing pulses and in which each of the input-output means includes means for counting the timing pulses on the timing bus and means responsive to a predetermined count of the timing pulses for connecting its respective sub-system to the communications bus.
 4. The text processing system of claim 1 in which the communications bus includes a data bus section and in which the input-output section of each of the sub-systems which receives or provides signals indicative of text includes means for connecting its respective sub-system to the communications bus during predetermined portions of the cycle of timing signals.
 5. The text processing system of claim 1 in which the communications bus includes a control and indicator bus section and in which the input-output section of each of the sub-systems which receives or provides signals indicative of control and indicator terms includes means for connecting its respective sub-system to the control and indicator bus during predetermined portions of the cycle of timing signals.
 6. The text processing system of claim 1 in which the communications bus includes an address and command bus section and in which the input-output section of each of the sub-systems includes means for connecting signals indicative of address and command instructions between its respective sub-system and the address and command bus at all times during the cycle of timing signals. 